Display Module Interfaces Explained | 8080, 6800, SPI, I2C, RGB

The 8080 parallel port gains high bandwidth by utilizing 8/16-bit lines, SPI reaches high-speed serial communication at 50MHz, I2C saves on pins, and RGB relies on VSYNC synchronization to support 60Hz and 24-bit color.

8080

It supports data widths of 8-bit, 16-bit, or 18-bit. The main frequency typically operates between 6MHz and 20MHz.

Compared to SPI, its transmission volume is larger, as a single signal pulse can carry complete color pixels.

Relying on independent WR and RD lines, the system can quickly access the memory inside the display IC.

It is often paired with ICs like the ILI9341 for LCDs with resolutions of 320*240 or 480*320.

Signal Pin Distribution

The arrangement of its data bus, DB0 to DB17, determines the color depth the display module can support.

In 8-bit bus mode, only the DB0 to DB7 pins are used in hardware, while the remaining high-order pins are typically grounded through 10k-ohm resistors to reduce noise interference.

In this mode, transmitting one 24-bit True Color (RGB888) pixel requires the master controller to perform three consecutive write operations.

In a 16-bit bus configuration, pins DB0 to DB15 are fully connected, allowing an RGB565 format pixel to be written in a single pulse, which reduces the instruction cycle overhead of the master controller.

In an 18-bit configuration, pins DB0 to DB17 are mapped to the internal 6-bit registers for each of the R, G, and B components within the driver chip.

The voltage standard for data lines typically follows the VDDI specification, with common ranges between 1.65V and 3.3V.

During PCB design, the length deviation of related data lines should be controlled within 5mm.

Frequencies above 10MHz can cause phase shifts; if 16-bit data does not arrive simultaneously, noise will appear on the screen.

Signal Name	Functional Description	Electrical Characteristics	Suggested Physical Impedance
DB[17:0]	Parallel Data Bus	VIL < 0.3 * VDDI, VIH > 0.7 * VDDI	50 Ohm
CS	Chip Select (Active Low)	Input capacitance controlled below 10pF	100 Ohm
RS / DC	Register Select	High for RAM data, Low for Command	100 Ohm
WR	Write Strobe Pulse	Min pulse width 15ns (e.g., ILI9341)	33-100 Ohm series resistor
RD	Read Strobe Pulse	Access delay range 45ns to 340ns	33 Ohm series resistor
RESET	Hardware Reset	Pulse width must be > 10us	N/A

The definition of control bus pins is strict. The CS pin is responsible for module selection. When multiple peripherals share a single bus, multi-slave communication is achieved by controlling the CS level.

The RS pin (also labeled as D/CX in some specifications) determines whether the information entering the data bus is parsed as a control register address or filled into the display memory.

The WR pin is usually connected to the master controller's write strobe signal. Data latching occurs at the rising edge of the WR signal.

At the hardware level, the driving current for the WR line usually needs to reach 4mA or more to ensure the signal waveform does not undergo severe distortion under high-speed switching.

The RD pin is used less frequently, primarily for reading the display driver ID, the current scan line position, or reading back GRAM content for comparison and analysis.

The timing requirements for read operations are more relaxed than for writes.

The low-level duration of RD is generally more than three times that of WR, allowing enough time for the driver circuit inside the display chip to push charge to the data bus pins.

VDD (or VCC) is responsible for the internal analog circuits of the driver chip and the LCD panel driving voltage, with typical values between 2.8V and 3.3V.

VDDI (or VCCIO) specifically powers the interface circuits, and its voltage level must strictly match the IO level of the master controller.

If the master controller uses 1.8V logic but VDDI is mistakenly connected to 3.3V, it will cause an input logic threshold mismatch at the interface, resulting in a large number of bit errors during signal transmission.

The RESET pin circuit design typically includes a simple RC delay circuit. Although most driver chips have a software reset function, the hardware reset pin provides a reliable physical initialization channel.

In the first 20ms after system power-up, the RESET pin should remain low until the supply voltage stabilizes above 90% of the rated value.

Operation Type	Parameter Symbol	Ref. Value (ns)	Environment Condition
Write Cycle Time	tWC	66	VDDI = 2.8V
Address Setup Time	tAST	0	Aligned with WR falling edge
Address Hold Time	tAHT	10	Maintained after WR rising edge
Read Cycle Time	tRC	450	When reading GRAM data
Read Access Time	tACC	340	Time for data to appear on bus
Read Data Hold Time	tRDH	20	Time before data disappears after RD High

Taking 16-bit bus RGB565 pixel transmission as an example, DB15-DB11 handles the Red channel (R), DB10-DB5 handles Green (G), and DB4-DB0 handles Blue (B).

If an 8-bit bus is used, the first byte transmits R4-R0 plus G5-G3, and the second byte transmits G2-G0 plus B4-B0.

For an 18-bit bus, the color depth increases to RGB666, where each primary color uses 6 signal lines. This allocation method provides 262,144 colors, improving the grayscale transition performance of the image.

In electrical characteristics, the boundary values for Input High Level (VIH) and Input Low Level (VIL) are the basis for evaluating signal integrity.

Typically, the lower limit of VIH is 0.7 * VDDI, and the upper limit of VIL is 0.3 * VDDI.

At a signal rate of 10MHz, the Rise Time (tr) and Fall Time (tf) should generally be controlled within 15ns.

If the parasitic capacitance of the traces is too large, the waveform will slow down, shortening the Data Setup Time (tDST) and causing errors.

For instance, in the commonly used ILI9488 chip, the minimum write pulse width required is 15ns, which theoretically means a maximum write frequency of about 33.3MHz.

However, in actual engineering, considering system margin, it usually runs in the 10MHz to 20MHz range.

Read/Write Logic

Before initiating a write operation, the master controller must first pull the CS signal low to move the display driver IC out of the high-impedance state and into the controlled state.

Subsequently, the level of the RS signal determines the attribute of the current transmission: when RS is low, the binary values on the bus are redirected to the Instruction Register (IR) to set scan direction, clock frequency, or sleep mode; when RS is high, the data flows into the Frame Memory (GRAM).

During the signal establishment phase, the voltages on the data bus DB0 to DB17 must stabilize before the falling edge of the WR signal.

This interval is called the Data Setup Time (tDST).

In the standard ILI9341 driver specification, this value usually must not be lower than 10ns.

Physical latching actually occurs at the moment of the rising edge jump of the WR signal from low to high, where the sample-and-hold circuit inside the driver chip captures the bus level.

To ensure data is correctly identified, the low-level pulse width of the WR signal (tPWLW) must meet the minimum requirement of 15ns, and after the rising edge, the bus data must be maintained for at least 10ns (tDHT) to prevent errors caused by signal reflection.

• Physical Steps of a Write Sequence:
  1. The master controller IO port outputs the target address or pixel data to the parallel bus; the driving current must overcome the parasitic capacitance of the PCB traces.
  2. The RS signal switches level according to the task (command or data) and remains stable.
  3. CS signal is pulled low, activating the internal bus interface logic of the module.
  4. WR signal generates a low pulse with a width of 15ns to 50ns; the driver chip captures the bus state at the trailing edge of the pulse.
  5. After WR returns to high, the data bus voltage can be removed in preparation for the next cycle.
  6. The CS signal is pulled high after continuous write tasks end, releasing bus control.

In read operations, the RD (Read Strobe) signal replaces the function of WR.

When the RD signal is pulled low, the display driver IC takes over the drive of the data bus, pushing data from the internal status registers or GRAM through the output buffers onto the bus.

Because the internal read delay of the driver chip is relatively large, the master controller must wait for an interval called Read Access Time (tACC) after pulling RD low before it can obtain valid data on the bus.

For the high-performance ST7789 driver, the access time for reading an ID is about 40ns, while the time to read pixel data from GRAM may extend to 340ns.

The cycle for reading pixels (tRC) is much larger than the write cycle (tWC), so extra Wait States are usually required in programming.

After the read process ends, the RD signal is pulled high, and the data pins of the driver chip return to a high-impedance state. This transition process (tOHZ) takes about 15ns to 80ns.

Timing Parameter	Symbol	Min Value (ns)	Electrical Impact
Write Cycle Time	tWC	66	Determines max write frequency (~15MHz)
Write Pulse High Width	tPWHW	15	Affects waveform recovery during continuous writes
Write Pulse Low Width	tPWLW	15	Min time for internal logic determination
Address Setup Time (RS to CS)	tAS	0	Ensures command/data are not confused
Data Setup Time (Write)	tDST	10	Compensates for delay caused by bus impedance
Read Access Time (ID Read)	tACC	40	Physical delay master must wait before sampling
Read Access Time (RAM Read)	tACCRAM	340	Limits the speed of reading images from screen

In 16-bit mode (with IM pins configured accordingly), a single write cycle can transmit a complete RGB565 pixel.

In this case, DB15 to DB11 carry the Red component, DB10 to DB5 carry Green, and DB4 to DB0 carry Blue.

If the system switches to 8-bit mode, the logic changes: the master controller needs to perform two consecutive write cycles to synthesize one 16-bit pixel.

The first write cycle transmits the high 8 bits of data, which the driver chip temporarily stores in an internal shadow register; the second write cycle transmits the low 8 bits.

At this point, the internal logic combines the two sets of data and writes them into the GRAM at once.

While this mechanism saves 8 IO pins, it effectively halves the total bus bandwidth required for screen refreshing.

• Comparison of 16-bit and 8-bit Bus Efficiency:
  • 16-bit Bus (RGB565): Refreshing a 320 * 240 screen requires 76,800 WR pulses.
  • 8-bit Bus (RGB565): Refreshing the same screen requires 153,600 WR pulses, a 100% increase in bus occupancy.
  • Bandwidth Calculation: At a 10MHz clock, 16-bit mode bandwidth is 160Mbps, while 8-bit mode is only 80Mbps.
  • Current Consumption: Due to the increased switching frequency, the dynamic power consumption (P = C * V^2 * f) of the interface in 8-bit mode is usually higher than in 16-bit mode at the same frame rate.

In high-speed data exchange via the 8080 interface, the Slew Rate of the WR and RD signals should be controlled above 1V/ns.

If the traces are too long, causing distributed capacitance to exceed 30pF, the rising edge of the WR signal will slow down, causing the display chip to fail data sampling within the scheduled time, manifesting as random wrong pixels on the screen.

To mitigate this, matching resistors of 22 ohms to 100 ohms are typically connected in series near the master controller endpoints to absorb signal reflections.

Additionally, the RS signal must be in place at least 10ns before CS is pulled low.

If RS is switched while CS is already low, some sensitive driver chips might misinterpret the logic, erroneously writing a command byte into the GRAM, leading to screen offsets or abnormal scrolling.

Operation Mode	RS Level	CS Level	WR/RD Status	Internal Data Flow
Command Write	Low	Low	WR Rising Edge Valid	System Command Register
Data/Pixel Write	High	Low	WR Rising Edge Valid	Frame Buffer (GRAM)
Status Read	Low	Low	RD Active Low	Status Register -> Bus
Pixel Readback	High	Low	RD Active Low	GRAM -> Bus Output Buffer

For continuous transmission of large volumes of image data, 8080 logic is usually used in conjunction with the master controller's DMA (Direct Memory Access) function.

By mapping the display interface to a specific memory address space, the master controller can synchronize the WR signal with the bus controller's write enable signal.

In this mode, the CPU does not need to simulate timing via software; instead, the hardware automatically generates WR pulses, pushing the pixel throughput to its physical limit.

At this point, the factor limiting the refresh rate shifts from CPU processing speed to the 8080 interface's tWC (Write Cycle Time).

For example, if the driver chip's tWC is 66ns, it can theoretically complete 15,151,515 16-bit writes per second, supporting a 320 * 480 resolution screen running at approximately 98Hz refresh rate.

However, in practical applications, due to DMA bus contention and internal GRAM write delay limitations, the operating frequency is usually set between 8MHz and 12MHz to ensure the robustness of logic determination across various ambient temperatures.

Transmission Performance Data

In the field of embedded displays, typical write cycles for common driver chips like ILI9341 or ST7789 usually range between 66ns and 150ns.

When the master controller is configured for 16-bit parallel mode and the write cycle is set to 66ns, the equivalent operating frequency of the interface is about 15.15MHz.

Since each pulse can transmit a complete pixel data (RGB565 format) in 16-bit mode, its raw physical layer bandwidth can reach 242.4 Mbps.

In comparison, a traditional 4-wire SPI interface, even running at a high frequency of 40MHz, requires 16 clock cycles to transmit the same 16-bit pixel due to its serial nature, resulting in an effective pixel bandwidth of only 40Mbps / 16 = 2.5MHz pixel rate.

When hardware design is limited by IO resources and adopts 8-bit mode, transmitting one RGB565 pixel must be done in two steps: the first write for high 8 bits (Red-Green components) and the second for low 8 bits (Green-Blue components).

At the same 10MHz clock, the pixel transmission rate of 8-bit mode drops to 5MHz, and the physical time to refresh the same 320 * 240 screen doubles to 15.36 milliseconds.

If the display content is upgraded to 18-bit True Color (RGB666) and the bus width remains 8 bits, three consecutive write pulses are needed to synthesize one pixel, tripling the total time.

In this mode, the bandwidth is diluted to about 26.6Mbps. For higher resolution display modules, such as a 480 * 320 HVGA screen where pixels increase to 153,600, the transmission pressure on the 8-bit bus increases significantly, easily leading to screen tearing.

The write pulse width (tPWLW) of the WR strobe signal is required to be no less than 15ns in most driver chip manuals, while the Data Setup Time (tDST) must be maintained above 10ns.

If distributed capacitance from PCB traces causes a decrease in signal rising edge slope, the master controller must artificially extend the write cycle to ensure the signal voltage reaches the 0.7 * VDDI logic high threshold.

At a 2.8V operating voltage, if bus capacitance exceeds 30pF, the rising edge time of the WR signal may increase from 5ns to over 15ns, forcing the system's stable write cycle toward 120ns or higher, thereby reducing overall bandwidth utilization.

To maintain high-speed transmission, hardware designs often include 22-ohm matching resistors in series near the master end to absorb reflections generated by high-speed edges.

For RGB666 pixel transmission under an 18-bit bus configuration, the theoretical bandwidth can reach 270Mbps at a 15MHz frequency.

Due to the read speed limitations of the memory array in the display chip's GRAM, the read cycle (tRC) often requires 450ns or longer, which is more than 6 times the write cycle.

The access time (tACC) for reading ID registers is about 40ns, but the access time (tACCRAM) for reading back pixel data usually requires around 340ns.

This makes the 8080 interface's read phase a bottleneck for overall speed when "Read-Modify-Write" operations are needed (such as performing complex transparency blending or layer stacking).

When designing high-performance UI libraries, developers usually allocate a shadow buffer (Frame Buffer) in the master's SRAM to avoid reading back GRAM data directly through the 8080 interface.

Since the 8080 interface is based on asynchronous communication with level flipping, its power consumption follows the basic law of P = C * V^2 * f.

In 16-bit mode, if a full white screen is displayed (frequent data line flipping) and it runs at 15MHz, the current consumption of the interface circuit may reach between 5mA and 15mA (depending on load capacitance).

In contrast, while 8-bit mode has fewer pins, it often has higher dynamic power consumption at the same frame rate because it requires twice the flipping frequency to maintain the same display effect.

In a 1.8V IO voltage environment, the estimated dynamic power consumption of a 16-bit bus at 10MHz is about 3.5mW.

Such hardware modules can map the display module as a block of static memory, automatically generating CS, RS, WR, and RD timings that comply with the 8080 protocol.

Under this hardware acceleration, the master controller only needs to execute a single memory write instruction (e.g., *LCD_ADDR = ColorData), and the hardware logic can complete the physical layer interaction within 66ns.

This method greatly optimizes data density, allowing the CPU to free up clock cycles to handle complex touch algorithms or GUI graphics rendering.

When evaluating display solutions, it is necessary to compare the efficiency difference between software-simulated IO (Bit-banging) and hardware controllers: the former may only achieve a 1MHz effective write speed at a 72MHz clock, while the latter can easily reach the physical speed limit of the driver chip.

6800

The standard includes 8-bit parallel data lines and three control signals: RS, R/W, and E.

Its physical layer logic is based on high-level pulse triggering of the E signal.

For a typical controller like the Hitachi HD44780 under 5V power supply, the E pulse width must be at least 140ns, and the address setup time no less than 40ns.

This interface switches read/write direction via a single R/W pin, with logic states locked by the E signal edge, adapting to early 68-series microprocessors.

Signal Definition

A standard 6800 parallel interface typically uses a 14-pin or 16-pin (including backlight) connector configuration, with a pin pitch of 2.54mm.

Power pins VSS and VDD correspond to logic ground and logic positive supply, with operating voltages usually between 2.7V and 5.5V.

For industrial-grade character LCD modules, the typical VDD value is 5.0V, with the logic high threshold not lower than 70% of VDD, and the logic low level controlled below 0.6V.

V0 (or VEE) is the contrast adjustment pin. The input voltage of this pin usually varies between 0V and 5V, adjusted via an external potentiometer to change the bias voltage of the LCD driver, thereby adjusting the darkness of the display characters.

In wide-temperature applications, V0 may even require a negative voltage input to maintain display clarity at low temperatures.

Backlight pins LED+ and LED- usually require a constant current drive of 20mA to 100mA, with the anode voltage drop floating between 3.0V and 4.2V depending on the backlight color (e.g., green, white, or blue).

Pin No.	Symbol	Signal Description	Physical Function
1	VSS	0V Ground	System reference ground
2	VDD	3.3V / 5.0V	Logic drive power input
3	V0	Bias Voltage	LCD contrast adjustment level
4	RS	Register Select	Instruction (0) or Data (1) register select
5	R/W	Read / Write	Read (1) or Write (0) direction control
6	E	Enable	Operation enable strobe pulse signal
7-14	DB0-DB7	8-bit Bus	Bi-directional tri-state parallel data bus
15	LED+	Backlight +	Backlight anode (requires resistor)
16	LED-	Backlight -	Backlight cathode (GND or PWM)

When RS is at logic 0, the codes transmitted over the DB0 to DB7 bus are sent to the internal Instruction Register (IR) of the controller chip, such as the clear screen command 0x01 or cursor move configurations.

When RS is at logic 1, the bus transmits pixel information or character ASCII codes to the Data Register (DR).

The microprocessor must stabilize the RS signal before operation; the address setup time tAS is usually required to be held for at least 40 to 60 nanoseconds before the rising edge of the E signal.

The R/W read/write control line dictates the physical direction of data flow. In the 6800 protocol, when R/W is set high, the module pushes internal status words (like the Busy Flag) or GRAM content onto the bus for the MCU to read.

When R/W is set low, the bus is in a high-impedance input state or driven by the MCU, preparing to store data into the module.

This single-line direction control design means 6800 uses one fewer control line than the Intel 8080 interface, but it demands higher timing synchronization.

The E (Enable) signal is the core clock reference for the 6800 interface, manifested physically as a high-level pulse.

All read and write actions occur only during the high period of the E signal or at its falling edge.

In write operations, the signals on data bus DB0 to DB7 must remain stable at the instant the E signal changes from high to low.

If the E signal pulse width PWEH is lower than 140ns (using the HD44780 typical value at 5V as an example), the internal logic gates of the display module may fail to correctly latch the levels on the bus, resulting in garbled displays or command failures.

During read operations, the module pushes data onto the bus within tDDR time (usually less than 160ns) after E goes high, at which point the MCU must sample the bus state until E returns to low.

Timing Parameter	Symbol	5V Min/Max Value	3.3V Ref. Value
Enable Cycle Time	tCYC	500 ns (min)	1000 ns (min)
Enable Pulse Width	PWEH	140 ns (min)	450 ns (min)
Enable Rise/Fall Time	tR / tF	25 ns (max)	25 ns (max)
Address Setup Time	tAS	40 ns (min)	60 ns (min)
Address Hold Time	tAH	10 ns (min)	20 ns (min)
Data Setup Time	tDSW	80 ns (min)	195 ns (min)
Write Data Hold Time	tH	10 ns (min)	10 ns (min)
Read Data Delay Time	tDDR	160 ns (max)	360 ns (max)

In 8-bit mode, all display instructions and 8-bit character codes are completed at once via these 8 lines.

However, to save MCU IO resources, the 6800 protocol supports a 4-bit mode. In 4-bit mode, DB0 to DB3 are ignored or grounded, and communication uses only DB4 to DB7.

The microprocessor must split an 8-bit byte into a High Nibble and a Low Nibble, sending two E pulses sequentially to complete the transmission of a full byte.

While this halves the communication efficiency, it saves 4 physical wires, which is very common in small microcontroller systems.

The input leakage current on the data lines is extremely small, usually around 1 microampere, and the output drive capability is sufficient for load capacitances below 100 picofarads.

In high-speed MCU systems, because the physical response of the 6800 interface is slow, software delays or polling the Busy Flag (status of DB7) are usually required in the code to ensure the previous instruction has finished processing inside the module.

When the Busy Flag is 1, the module is executing an internal operation (e.g., clearing the screen takes 1.52ms), and all write operations will be ignored at this time.

Physical Timing Quantization

The communication logic of this interface depends on the level transition of the enable signal E, rather than simple edge triggering.

In a complete write cycle, the enable cycle time tCYC is the most basic metric.

For a common 5.0V drive system, the lower limit of tCYC is usually set at 500ns, limiting the theoretical maximum bus transmission frequency to about 2MHz.

If the operating voltage drops to 3.3V or lower, the charge accumulation slows down due to the increased on-resistance of the drive transistors, and tCYC often needs to be relaxed to over 1000ns.

The enable pulse width PWEH specifies the shortest duration for which the E signal must stay high. In standard industrial modules, this value needs to reach 140 nanoseconds.

• Address Setup Time tAS: Specifies the minimum time RS and R/W signals must remain stable before the rising edge of E arrives; typical values are 40 to 60ns.
• Address Hold Time tAH: Refers to the duration RS and R/W must stay on the bus after E jumps back to low; standard requires no less than 10ns.
• Data Setup Time tDSW: The most critical parameter in write operations, requiring the microprocessor to stabilize the voltage on DB0-DB7 within logic thresholds 80ns before the falling edge of E occurs.
• Write Data Hold Time tH: Ensures that data remains present for 10ns after E goes low, allowing internal circuits to complete physical charge injection.
• Read Data Delay Time tDDR: Describes the lag from pulling E high to valid logic levels appearing on the bus during a read operation, usually around 160ns.

Signal rise time tR and fall time tF are also strictly limited, generally required to be within 20ns or 25ns.

If the E signal waveform becomes dull or rounded due to excessive trace capacitance, the slower slope increases logic determination uncertainty and may even trigger multiple erroneous read/write actions.

In scenarios of continuous multi-byte writing, logic timing constraints from instruction execution time must be considered alongside microsecond physical timing.

For example, a standard write data command usually takes 37 microseconds to process, while a clear screen command takes 1.52ms. During these times, the module cannot receive new data even if the physical layer meets the 500ns cycle.

In such cases, the status of pin DB7 as the Busy Flag becomes the quantitative basis for microprocessor polling.

After the E signal transitions high, internal drive circuits start driving current to the parallel bus to charge the DB0-DB7 data lines. tDDR may extend to 360ns in a 3.3V system; the MCU's I/O sampling window must shift backward, or it will read false data from a floating bus state.

When the read ends and E goes low, the bus release time tDHR specifies the speed at which the bus returns to a high-impedance state, generally between 5 and 100 nanoseconds.

• Enable Cycle Time (Write): 500ns (5V) / 1000ns (3V)
• Enable Cycle Time (Read): 1000ns (5V) / 1200ns (3V)
• E Pulse Width (High Level): 140ns (5V) / 450ns (3V)
• E Pulse Width (Low Level): 140ns (5V) / 450ns (3V)
• RS to E Setup Time: 40ns or more
• Data to E Setup Time (Write): 80ns or more
• E to Data Valid Time (Read): Max 160ns (5V) / 360ns (3V)

In actual PCB debugging, the 10 to 15 picofarad load capacitance introduced by probes can interfere with these nanosecond-level observations.

Hardware designers must ensure the drive source current can overcome these parasitic parameters to maintain sharp signal edges.

For high-speed microprocessors with clock frequencies exceeding 100MHz, the pulse width generated by direct GPIO operation is often far below the 140ns requirement.

In these cases, No-Operation (NOP) instructions must be inserted at the firmware driver layer, or hardware wait cycles must be used to artificially stretch the E signal width.

Without such compensation, waveforms observed on logic analyzers may show severe signal overshoot or undershoot, leading to RS signal level drift during the valid E period, which causes character displacement or random pixels on the display.

SPI

Under 3.3V logic levels, its clock frequency typically runs between 20MHz and 80MHz.

Taking a 240 * 320 resolution screen as an example, when using 16-bit color depth (RGB565), the single-frame data volume is 153.6KB.

At a 40MHz frequency, the theoretical transmission time is about 31 milliseconds, supporting around 30 frames per second.

Physical Pin Definition

For common display interfaces, power pins are usually divided into analog power (VCI/VCC) and digital interface power (IOVCC).

VCI provides 2.8V to 3.3V to drive internal analog circuits, charge pumps, and bias voltage sources, while IOVCC adapts to the processor's logic level, usually between 1.65V and 3.3V.

To suppress high-frequency noise, each power pin typically needs 0.1uF and 10uF ceramic capacitors in parallel near the module.

Ground lines (GND) should be as wide as possible to lower the return path impedance, preventing high-speed clock signals from generating electromagnetic interference or waveform distortion.

In serial interfaces (SPI/I2C), the clock pin (SCLK/SCL) is the reference for all communication.

For SPI, SCLK frequencies range from 10MHz to 80MHz. Physically, this line must maintain impedance matching, usually designed with a 50-ohm characteristic impedance.

If the wiring is too long, the signal's rising and falling edges will show overshoot or ringing, leading to data latching errors. Data pins (MOSI/SDA) are sampled at the rising or falling edge of the clock.

A key differentiator in SPI interfaces is the D/C (Data/Command) pin. When low, the transmission consists of 8-bit register addresses or commands; when high, it consists of 16-bit (RGB565) or 24-bit (RGB888) color pixels.

The CS (Chip Select) pin must remain low throughout the communication; its falling edge triggers the internal timing reset of the driver chip.

Pin Category	Signal Name	Electrical Characteristic	Functional Description
Control Bus	CS (Chip Select)	Active Low	Activates display module and internal logic.
Clock Bus	SCLK / PCLK	10MHz - 100MHz	Determines throughput; needs signal integrity.
Data Bus	D0 - D15	CMOS Logic Level	Pixel data; bit width affects bandwidth.
Status Switch	D/C (RS)	0:CMD / 1:DATA	Indicates data type; controls state machine.
Read/Write	WR / RD	Pulse Width > 15ns	Triggers data write or read operations.
Hard Reset	RESET	Active Low	Clears registers, initializes timing.
Backlight	LEDA / LEDK	20mA - 120mA	Controls LED current; paired with PWM.

In 16-bit 8080 parallel mode, WR (Write Enable) and RD (Read Enable) pins control the bus direction.

When WR generates a low pulse (min width 15-50ns), the driver chip captures the D0-D15 levels on the WR rising edge.

The bandwidth of this mode is far higher than serial interfaces; at a 20MHz write cycle, it can transmit over 320MB of data per second.

However, the large number of pins requires significant PCB space, and the skew between data lines must be within 50mil to ensure synchronization.

The HSYNC signal informs the display of the start of a pixel row, while VSYNC marks the start of a frame.

RGB interfaces usually require 16 to 24 data lines. For stable display, Front and Back Porch parameters must be configured.

For example, HBP (Horizontal Back Porch) and HFP (Horizontal Front Porch) define invalid pixel periods before and after the row sync signal, where PCLK toggles but the DE pin remains low.

Backlight pins, though not part of data communication, are critical. LEDA (anode) and LEDK (cathode) connect to the internal LED array.

For a ~3.5-inch screen, 6 to 10 LEDs are usually needed, driven at ~20mA with a forward voltage drop (Vf) up to 15V-25V.

PCB design should keep backlight power lines away from sensitive analog lines to prevent switching noise from the boost circuit.

Some modules also lead out a TE (Tearing Effect) pin to synchronize refreshes and prevent tearing when the controller rate mismatch occurs.

Communication Mode Differences

4-wire SPI mode uses an additional physical pin, D/C (Data/Command), to distinguish between commands and pixel data.

In this mode, data is transmitted in a standard 8-bit format.

When D/C is low, the display identifies data as a register address; when high, it identifies it as parameters or color values.

This physical separation significantly reduces software overhead for the MCU, as most hardware SPI controllers natively support 8-bit buffers.

At a 40MHz clock, an 8-bit transmission takes 200ns. With no extra protocol bit burden, the effective link utilization is 100%.

In contrast, 3-wire SPI mode eliminates the D/C control line to further streamline pins. It embeds the "Command/Data" flag directly into the serial stream, forming a 9-bit transmission format.

A flag bit is sent at the very front of each packet: 0 for command, 1 for pixel.

This creates a physical challenge because most general-purpose MCUs only support 8-bit or 16-bit word lengths.

If using an MCU without 9-bit hardware acceleration, engineers must use GPIO bit-banging.

On a 100MHz processor, software SPI rates often reach only 1-5MHz, meaning a 240x320 screen frame takes over 300ms, resulting in visible lag.

From a density perspective, 3-wire mode has an 11.1% protocol overhead since an extra bit is added for every 8 bits of data, reducing overall throughput in bandwidth-limited scenarios.

Comm. Mode	Physical Pins	Packet Width	Hardware Compatibility	Protocol Overhead	Bandwidth Utilization
4-wire SPI	4 (CS, SCLK, MOSI, D/C)	8-bit	Very High (Std SPI)	0%	100%
3-wire SPI	3 (CS, SCLK, MOSI)	9-bit	Lower (Needs 9-bit)	11.1%	88.9%
Dual SPI	4 (CS, SCLK, IO0, IO1)	8-bit (Dual)	Medium (Needs QSPI)	0%	200% (vs. Single)
Quad SPI	6 (CS, SCLK, IO0-IO3)	8-bit (Quad)	Medium (Needs QSPI)	0%	400% (vs. Single)

Most display driver chips default to Mode 0 (CPOL=0, CPHA=0) or Mode 3 (CPOL=1, CPHA=1).

In Mode 0, the clock stays low when idle, sampling data on the SCLK rising edge and switching on the falling edge.

In Mode 3, the clock is high when idle, sampling also on the rising edge. For high-speed communication, Setup Time and Hold Time are very strict.

For example, some high-performance drivers require data to be stable at least 10ns before the clock edge.

If the frequency reaches 60MHz, the clock cycle is only 16.6ns; any trace impedance mismatch will shift the sampling point, causing noise or command loss.

To handle high resolutions (e.g., 480x800), Dual SPI and Quad SPI modes have emerged.

These don't change the sync logic but increase bandwidth by adding parallel data lines. Dual SPI uses two lines (IO0, IO1) to send 2 bits per cycle. Quad SPI uses four lines for 4 bits per cycle.

At 80MHz, Quad SPI theoretical bandwidth can reach 320Mbps.

1. Impact of Color Depth on Transmission Cycles:
   • In RGB565, each pixel takes 16 bits. Single-line SPI at 20MHz takes 800ns per pixel.
   • In RGB888, each pixel takes 24 bits. At 20MHz, the cycle extends to 1200ns.
2. Frame Rate vs. Resolution Quantification:
   • A 1.3-inch round screen (240x240) has 921,600 bits per 16-bit frame.
   • Using 30MHz 4-wire SPI, the max frame rate is ~32.5 FPS.
   • Switching to 3-wire 9-bit mode at 30MHz, the frame rate drops to ~29 FPS.
3. Electrical Constraints:
   • SPI signals over 20cm may have overshoots exceeding 0.5V due to inductance.
   • At high frequencies, 22-47 ohm resistors must be in series to absorb reflections.

Though displays are mostly receiving, communication switches to half-duplex when reading registers or IDs.

Some modules merge MOSI and MISO into one bi-directional SDA line, requiring the controller IO to switch directions quickly.

Read operations usually require a "Dummy Clock" (1 to 8 cycles) for internal analog circuit preparation.

Data Bandwidth Measurement

For a typical display system, the total bits per frame is Resolution (W * H) * Bits Per Pixel (BPP). Taking a 240 * 320 screen in RGB565 (16-bit) mode, a frame is 76,800 pixels, totaling 1,228,800 bits.

If the SPI frequency is 40MHz (40,000,000 bps), the theoretical limit is 32.5 FPS. However, actual bandwidth is usually 80%-90% of theoretical after deducting CS switching, command bytes, and driver row processing delays.

At a 20MHz clock, a 153.6KB frame (240x320 RGB565) takes 61.44ms. This limits the refresh rate to ~16 FPS, causing visible tearing or frame drops during fast motion or scrolling.

In RGB666 mode, each pixel needs 18 bits, but in SPI it is often padded to 24 bits (3 bytes) to align with 8-bit memory units.

In 24-bit mode, data volume increases by 50% over 16-bit. For a 320x480 screen, 24-bit color data reaches 3,686,400 bits. At 50MHz, the theoretical rate is only 13.5 FPS.

Improving SPI bandwidth depends not just on SCLK frequency but also on MOSI parasitic capacitance. At an extreme 80MHz, each bit pulse is only 12.5ns. PCB trace inductance can distort the waveform. If Setup Time falls below 5ns, the driver won't latch data accurately, causing screen noise.

In 4-wire SPI, the D/C pin is independent, so no protocol bits occupy the pixel stream.

However, in 3-wire 9-bit SPI, an extra bit is added before every 8-bit pixel byte, requiring a 1.125 penalty coefficient.

A 240x320 screen that reaches 32.5 FPS at 40MHz in 4-wire will drop to 28.9 FPS in 9-bit mode.

I2C

The hardware layer uses only SDA (Data) and SCL (Clock). The protocol supports 7-bit and 10-bit addressing, with rates of 100kbps (Standard), 400kbps (Fast), and up to 3.4Mbps (High-Speed).

The bus uses an open-drain output, requiring 1k to 10k ohm pull-up resistors.

In display, it often drives SSD1306 or SH1106 controllers, serving as the mainstream solution for pin-constrained scenarios.

Minimal Hardware Layout

In traditional parallel interfaces (e.g., 8080), the master needs to allocate at least 8 data lines and 4-5 control lines (RS, WR, RD, CS, RESET), consuming over 13 GPIO ports.

In contrast, I2C compresses pins to the extreme, enabling full graphics display on small packages (e.g., 8-pin or 16-pin MCUs).

Master and display driver output drivers do not actively push signals high; they only pull them down to GND.

To maintain a high state when idle, pull-up resistors (Rp) must be on SDA and SCL, connected to VDD.

Parameter	Standard (100 kbps)	Fast (400 kbps)	High-Speed (3.4 Mbps)
Max Rise Time	1000 ns	300 ns	80 ns
Typical Rp	4.7k - 10k Ohm	2.2k - 4.7k Ohm	1k Ohm
Max Cb (Capacitance)	400 pF	400 pF	100 pF
Operating Current	Lower	Medium	Higher

In 3.3V systems with 2.2k resistors, a low SDA creates 1.5mA of current.

Sensitive systems might use 10k resistors, but this stretches rise time and may cause errors at 400kbps.

Total bus capacitance (Cb) includes PCB parasitic capacitance and input capacitance of all devices (typically 5-10pF per slave).

For a 0.96" OLED with an SSD1306, an SA0 (or DC) pin is usually provided for address selection. Connecting it to VCC or GND changes the 7-bit I2C address, allowing two identical screens on one bus.

Module Type	Addr Pin Status	7-bit Hex Addr	8-bit Op Code (R/W=0)
SSD1306 OLED	GND	0x3C	0x78
SSD1306 OLED	VCC	0x3D	0x7A
PCF8574 Board	All Floating/High	0x27	0x4E
SH1106 OLED	Fixed Internal	0x3C	0x78

SDA and SCL are sync signals; while length matching isn't as strict as RGB, they should be parallel.

Keep them away from high-frequency power or high-current traces to prevent crosstalk.

In 2-layer boards, a solid ground plane underneath is recommended.

If the module uses long FPC or jumper wires, inductance can cause overshoot; a 22-100 ohm series resistor at the master can absorb reflections.

Standard MOSFET-based bi-directional level shifters are needed for mixing 3.3V and 5V devices, ensuring safe communication without overvoltage damage.

Slave Addressing Mechanism

Physically, after pulling SDA low for a Start signal, the master sends an 8-bit control byte.

The first 7 bits define the Slave Address, and the 8th defines direction. This allows addressing up to 127 devices (excluding reserved addresses) on two wires.

Controllers like SSD1306 or SSD1327 have preset address bases. Addressing follows MSB first.

For most 0.96" or 1.3" OLEDs, the 7-bit address is 0x3C or 0x3D. The SA0 pin provides an offset: grounded for 0111100 (0x3C) or high for 0111101 (0x3D).

In software, 8-bit values are left-shifted: 0x3C becomes 0x78 for writes and 0x79 for reads.

7-bit Binary	Hex Range	Function	Behavior
0000 000	0x00	General Call	Broadcast reset/load commands to all devices
0000 001	0x01	Start Byte	Helps slow masters identify high-speed activity
0000 1XX	0x04 - 0x07	HS Mode Master Code	Used in high-speed mode switching
1111 0XX	0x78 - 0x7B	10-bit Addr 1st Byte	Extends addressing to 1024 nodes
1111 1XX	0x7C - 0x7F	Reserved	Reserved for future protocol extensions

After the master sends 8 bits and releases SDA, it waits.

If a display module identifies the address, it pulls SDA low during the 9th pulse to generate an ACK.

A high signal (NACK) means the address is absent or the module is busy. Polling ACK is common for checking connectivity.

In multi-master environments, arbitration occurs: since it is open-drain, a 0 (low) beats a 1 (release). If a master outputs 1 but sees 0, it exits.

Fast Mode (400kbps) requires SCL high time ≥ 0.6us and low time ≥ 1.3us. SDA changes must occur during low SCL.

During high SCL, SDA must be stable; any jump is misinterpreted as a Start/Stop condition, causing garbled display.

• SSD1306/SH1106 OLED: 7-bit address 0x3C or 0x3D, hardware-selectable.
• SSD1309 OLED: Fixed at 0x3C, no external pin modification.
• PCF8574 Adapter: Used for LCD1602, A0/A1/A2 jumpers allow 0x20-0x27.
• SSD1327 Controller: 128x128 grayscale, default address usually 0x3D.

Electrical Parameter Matching

The product of Rp and Cb determines the Rise Time (tr). Standard Mode (100kbps) requires tr ≤ 1000ns; Fast Mode (400kbps) requires tr ≤ 300ns.

Using 10k resistors on high-capacitance boards (e.g., 200pF) leads to tr > 400ns, causing sampling errors.

Reducing Rp helps tr but is limited by sink current (usually 3mA max at 0.4V). In 3.3V systems, resistors below 1k will exceed 3.3mA, preventing VOL from reaching logical zero and locking the bus.

CMOS display controllers typically have VIL max = 0.3 VDD and VIH min = 0.7 VDD.

The total load limit is 400pF. For multiple 1.3" OLEDs with long cables, capacitance rounds the square waves into sawteeth.

Min resistor value = (VDD - 0.4V) / 3mA. Max resistor value = tr / (0.8473 * Cb). 2.2k to 4.7k ohms cover most short-to-medium display connections.

Electrical Item	Symbol	Fast Mode (400kbps) Limit	Typical (3.3V, 2.2k Rp)
Low Output Voltage	VOL	Max 0.4 V (at 3mA)	0.15 V - 0.25 V
Low Input Voltage	VIL	Max 0.3 VDD (0.99 V)	~0.8 V (with margin)
High Input Voltage	VIH	Min 0.7 VDD (2.31 V)	2.8 V - 3.1 V
Rise Time	tr	Max 300 ns	120 ns - 180 ns
Fall Time	tf	Max 300 ns	10 ns - 40 ns
Bus Capacitance	Cb	Max 400 pF	50 pF - 150 pF

For mixing 1.8V and 5V devices, N-channel MOSFET level shifters are standard.

When the low-voltage side sends 0, the MOSFET conducts to pull the high-voltage side low; when sending 1, the MOSFET cuts off and the high side returns to 5V via its own pull-up. 

RGB

Since the panel lacks internal GRAM, the controller must push data in real-time at ~60Hz. For 800*480, the pixel clock is typically 33.3MHz excluding blanking areas.

This supports 16.7M True Color and directly operates the panel's source control circuitry, reducing panel BOM costs and increasing refresh rates.

Signal Channel Composition

Data width determines color precision; 24-bit RGB888 has 24 lines (R0-R7, G0-G7, B0-B7). PCB layout must follow equal-length rules (within 50mil) to prevent phase lag.

Information is sent on the PCLK (Pixel Clock). For 1024*600 at 60Hz, PCLK is ~45-51MHz.

Driver ICs sample on the PCLK edge. To reduce EMI and reflection, 22-33 ohm series resistors should be at the processor end for 50-ohm matching.

Signal Category	Name	Pins	Electrical Parameter & Definition
Pixel Clock	PCLK	1	5-150MHz; jitter < 300ps
Row Sync	HSYNC	1	Start of line; low pulse width 1-40 PCLK
Frame Sync	VSYNC	1	Start of frame; pulse width 1-10 lines
Data Enable	DE	1	High: valid pixel; Low: blanking area
Red Data	R0-R7	8	R0=LSB, R7=MSB
Green Data	G0-G7	8	G0=LSB, G7=MSB
Blue Data	B0-B7	8	B0=LSB, B7=MSB
Power/GND	VDD/GND	4-8	Digital/Analog split; drop < 50mV

VSYNC resets the IC to the top-left; HSYNC moves to the next row. The Blanking Period between these includes Front Porch, Sync Pulse, and Back Porch.

During HSYNC Back Porch, the source drive pre-charges for the next row. In DE Mode, sync may be simplified, relying on DE high level to lock valid pixels.

When DE is high, PCLK samples pixels; when low, data toggles aren't displayed. For 16-bit RGB565, unused low-order pins (R0-R2, G0-G1, B0-B2) are grounded.

• Avoid large filter capacitors on PCLK to prevent rounded waves and Setup/Hold time failures.
• Setup Time ≥ 5ns, Hold Time ≥ 2ns are physical minimums for correct latching.
• For FPC > 15cm, use buffers or differential signaling to suppress attenuation.
• Crosstalk: Follow the 3W rule (spacing ≥ 3x trace width).

Digital (VDD 3.3V) and Analog (AVDD ~10V for LC bias) power should be separate.

Near the FPC, use 0.1uF and 10uF ceramic capacitors to filter switching noise. VDD ripple > 100mV can cause flickering or color shifts.

Timing Detail Quantization

For 800x480, Total Pixels (Th) = 1056, Total Lines (Tv) = 525; at 60Hz, PCLK is 33.3MHz.

Blanking takes 10%-20% of bandwidth for charge reset and switching. HSYNC Back Porch (HBP) or Front Porch (HFP) allows the source drive to receive data.

If too small, pixels shift horizontally or cause edge artifacts. For 1024x600, typical HSPW=20, HBP=140, HFP=160 cycles.

A vertical cycle includes VSPW, VBP, VACT (Visible), and VFP. VSPW clears row address scanners.

VBP determines how many lines pass after VSYNC before valid data starts. Inaccurate vertical timing causes jumping or top color banding.

Category	Name	Abbr.	800x480 Typical	1024x600 Typical	Unit
Clock	Pixel Freq.	PCLK	33.3	51.2	MHz
Horizontal	Total Pixels	Th	1056	1344	Clocks
Horizontal	Valid Width	HACT	800	1024	Clocks
Horizontal	Sync Width	HSPW	48	20	Clocks
Horizontal	Back Porch	HBP	40	140	Clocks
Horizontal	Front Porch	HFP	168	160	Clocks
Vertical	Total Lines	Tv	525	635	Lines
Vertical	Valid Lines	VACT	480	600	Lines
Vertical	Sync Width	VSPW	3	3	Lines
Vertical	Back Porch	VBP	32	20	Lines
Vertical	Front Porch	VFP	10	12	Lines

Setup time (signal stability before PCLK jump) ≥ 5ns and Hold time (after jump) ≥ 2ns are critical.

High master frequencies without delay compensation lead to sampling in transition zones, causing noise. PCLK jitter must be < 300ps to prevent phase out-of-sync.

FPC > 10cm rounds waveforms, shrinking the Eye Diagram; use software Drive Strength or hardware buffers.

Polarity (Active High/Low) for VSYNC/HSYNC and PCLK edge (Rising/Falling) must match; wrong polarity results in black screens or irregular blinking.

Color Depth Mode Differences

16-bit (RGB565) mode uses 2 bytes per pixel for 65,536 colors. Green gets 6 bits (64 levels) because the eye is more sensitive to green luminance.

In resource-limited systems, this saves 1/3 bandwidth and memory. R/G/B levels are 32, 64, 32; large gradients may show visible banding (artifacts).

24-bit (RGB888) mode gives 8 bits (256 levels) per channel for 16.7M colors (True Color).

Each pixel is 3 bytes (or 4 bytes RGBx for alignment).

800x480 at 60Hz produces ~69.12MB/s in RGB888 vs. 46.08MB/s in RGB565.

24-bit removes banding and provides photo-level reproduction.

Mode	Bits (R:G:B)	Total Colors	Bytes/Pixel	Pins Needed
RGB565	5:6:5	65,536	2 Bytes	16 Data Lines
RGB666	6:6:6	262,144	2.25/3 Bytes	18 Data Lines
RGB888	8:8:8	16,777,216	3 Bytes	24 Data Lines
RGB101010	10:10:10	1,073,741,824	4 Bytes	30 Data Lines

18-bit (RGB666) is common in industrial modules (262k colors, 18 pins).

For compatibility, R7-R2 from a 24-bit master connect to R5-R0 of the screen; low bits R1/R0 are floating.

Connecting master low bits to display high bits causes non-linear distortion. 24-bit interfaces have ~28 pins and generate EMI at >70MHz PCLK; RGB565 reduces pins and complexity.

Dithering (e.g., FRC) allows lower-depth panels (18-bit) to simulate 24-bit visuals using temporal or spatial switching.