How PMOLED Works | Structure, Driving Method & Pixel Control

PMOLED utilizes an orthogonal matrix of anodes and cathodes, employing a progressive scanning method to instantaneously activate pixels with a 1/N duty cycle.

During operation, a voltage of approximately 15V is required to light up the intersections. It is recommended to limit applications to under 3 inches to balance the power consumption caused by high instantaneous brightness.

Structure

The bottom layer consists of transparent Indium Tin Oxide (ITO) anode strips etched onto a glass or plastic substrate.

Multiple layers of organic functional thin films are stacked in the middle, and the top layer consists of metal cathode strips arranged vertically at 90 degrees to the anodes.

This simple orthogonal arrangement removes the dependence on Thin Film Transistors (TFTs).

Taking a screen with a resolution of 96x64 as an example, the structure contains 96 vertical anodes and 64 horizontal cathodes.

The physical overlap area between the two directly defines 6,144 independent light-emitting pixels.

Vertical Layer Stacking

Glass Substrate Selection

For PMOLED devices, which are primarily used for low-cost, small-sized displays, 0.5 mm or 0.7 mm thick glass is the standard configuration.

Flatness Requirements: The flatness of the glass surface has a significant impact on yield. The root mean square (RMS) surface roughness must be controlled below 2 nanometers.
Refractive Index Matching: The refractive index of glass is usually around 1.5. When light generated in the organic layer enters the glass and then exits towards the air, approximately 50% to 60% of the light is trapped inside the glass substrate due to the total internal reflection effect, eventually dissipating at the edges without being seen by the user.

Anode Conductive Characteristics

Indium Tin Oxide (ITO) thin film is deposited on the glass. This is an n-type semiconductor material that possesses both high transparency (visible light transmission > 90%) and conductivity.

In the PMOLED structure, the sheet resistance of the ITO layer is a physical limiting factor.

Typically, the sheet resistance of ITO is between 10 to 20 ohms/square. Since PMOLED uses progressive scanning, current must flow through the long, thin anode strips instantaneously.

If the ITO lines are too long, the accumulation of resistance leads to a significant voltage drop (IR Drop).
This causes non-uniform brightness, where one end of the screen is bright and the other is dim. Therefore, it is difficult to make PMOLED screens large, and they are usually limited to under 3 inches. Part of the reason is that the conductivity of ITO is insufficient to support large current transmission over long distances. In the process, engineers usually perform UV-Ozone treatment on the ITO surface. This not only cleans the surface but also increases its work function from approximately 4.7 eV to about 5.0 eV, bringing it closer to the energy level of the hole transport layer above, which facilitates charge injection.

Hole Transport Channels

If these two layers are not added, the energy barrier for hole injection would be too high, forcing a significant increase in the driving voltage.

Hole Injection Layer (HIL): Directly covers the ITO, with a thickness of about 10 to 20 nanometers. Common materials include CuPc (Copper Phthalocyanine) or polymer PEDOT:PSS.
Hole Transport Layer (HTL): Located above the injection layer, with a thickness of about 40 to 60 nanometers. Common materials are NPB or TPD.

Light-Emitting Recombination Zone

The Emissive Layer (EML) is the heart of the entire sandwich structure, with a thickness usually between 20 to 40 nanometers.

Host Material: Accounts for more than 90%, responsible for energy transfer. For example, Alq3 (tris(8-hydroxyquinoline)aluminum) is often used as the host for green emission.
Dopant Material: The doping ratio is extremely low (1% - 5%), determining the color and efficiency of the light.

If traditional fluorescent materials are used, according to quantum statistics, only 25% of singlet excitons can emit light, while the remaining 75% of triplet energy is dissipated as heat, resulting in lower efficiency in early PMOLEDs.

Modern high-end materials have begun to introduce phosphorescent systems to utilize that 75% of energy, but fluorescent materials remain common in low-cost PMOLEDs.

Parameter	Fluorescent Materials	Phosphorescent Materials
Exciton Utilization	25% (Singlet)	~100% (Singlet + Triplet)
Common Applications	Low-end PMOLED	High-end AMOLED
Lifespan Stability	Extremely high (especially Blue)	Blue lifespan is still a challenge
Cost	Low	High (contains rare metals like Iridium)

Cathode Metal Contact

The topmost layer is the cathode, responsible for injecting electrons into the device.

Since the Lowest Unoccupied Molecular Orbital (LUMO) level of organic materials is high, metals with a very low work function are needed to "push" electrons in.

A dual-layer composite cathode structure is usually adopted:

Electron Injection Layer (EIL): Closely attached to the organic layer is an extremely thin layer of insulating salt, usually Lithium Fluoride (LiF), with a thickness of only 0.5 to 1.0 nanometer.
Metal Overlayer: A thicker layer of Aluminum (Al) or Magnesium-Silver alloy (Mg:Ag) is deposited on top, with a thickness of 100 to 200 nanometers.

Encapsulation and Environmental Isolation

Once exposed to moisture and oxygen, the cathode will oxidize and fail, organic materials will crystallize, and expanding black spots will appear on the screen.

The final step in the physical structure of PMOLED is encapsulation.

A recessed glass lid is typically used to cover the substrate.
The edges are sealed with UV-curable epoxy resin.
Inside the recess of the glass lid, a desiccant (Getter) must be attached, usually Calcium Oxide (CaO) or Barium Oxide (BaO) tablets. These desiccants act as chemical sponges, responsible for absorbing trace moisture remaining from the encapsulation process or penetrating over time, ensuring the device's lifespan can reach 10,000 to 30,000 hours.

Orthogonal Electrode Matrix

Physical Dimensions of Strips

On the glass substrate, engineers typically use photolithography to etch the ITO layer into extremely narrow strips.

For a typical 0.96-inch monochrome display with a resolution of 128 x 64, the width of each ITO anode strip is approximately between 100 to 200 micrometers, and the physical gap between strips is usually controlled at 10 to 20 micrometers.

Resistance Values of Conductive Materials

In the matrix structure, the column electrodes (anodes) and row electrodes (cathodes) use completely different materials, leading to significant physical differences in their conductive performance.

ITO Anode Impedance: Although ITO is transparent, its conductivity is far inferior to metal. Standard ITO thin film sheet resistance is about 10 to 30 ohms/square.
Metal Cathode Advantage: In contrast, row electrodes composed of aluminum or magnesium-silver alloy have a sheet resistance usually less than 0.5 ohms/square.

This resistance mismatch leads to a physical phenomenon: pixels at different positions on the screen, even with the same theoretical input voltage, will experience slight attenuation in actual voltage due to different transmission distances.

To correct the non-uniform brightness caused by high ITO resistance, driving circuit designs often require voltage compensation for distant pixels, though this is an external control; the structure itself exhibits distinct resistive characteristics.

Sustaining Transient High Voltage

Since PMOLED lacks storage capacitors to maintain charge, each pixel is lit for only a very short time in each frame.

Taking a 64-row screen as an example, each row is called a "scanning line." At a 60Hz refresh rate, the time for each frame is 16.6 milliseconds.

This 16.6ms is averaged across 64 rows, so the actual power-on time for each row is only about 0.26 milliseconds.

In this instant, the current must be massive and the brightness extremely high for the human eye to perceive normal brightness through persistence of vision.

If the screen requires an average brightness of 100 nits, then at a 1/64 duty cycle, the instantaneous brightness of the pixel at the moment it is lit must reach 6,400 nits.

This structure forces the organic layers and electrode contact surfaces to withstand transient driving voltages as high as 15 or even 20 volts, much higher than the 4 to 5 volts typically required by AMOLED.

Parasitic Capacitance Effects

In physics, this is a standard "parallel plate capacitor." The entire display screen is actually a huge grid composed of thousands of micro-capacitors.

For a 128 x 64 matrix, each data line (column) crosses with 64 scanning lines (rows), resulting in a considerable cumulative parasitic capacitance value, usually between several picofarads (pF) and dozens of pF.

When the driver chip attempts to switch voltages quickly to change pixel brightness, these parasitic capacitances resist changes in voltage, producing charge/discharge delays (RC Delay).

Charging Delay: Voltage takes time to rise, causing pixels to light up slowly.
Discharge Delay: Voltage takes time to fall, preventing pixels from turning off completely.

This capacitance effect limits the size and refresh rate of PMOLED. If the screen is made larger, strips become longer, and capacitance increases, the signal delay becomes severe enough to cause ghosting or blurring, which is the physical reason why large PMOLED panels are rarely seen.

Physical Resolution Limit

The simple physical connection of the orthogonal matrix essentially locks the resolution ceiling of PMOLED.

If an engineer tried to make a 1080p (1080 rows) PMOLED screen, the light-emitting time for each row would be only 1/1080 of the frame time.

To maintain visible average brightness, the instantaneous brightness would need to be over 1000 times the average brightness. This would have two physical consequences:

Material Burnout: Extremely high current density would generate massive Joule heat instantly, causing the organic materials to carbonize or degrade.
Voltage Breakdown: The required driving voltage might exceed the breakdown voltage of the thin films, leading to short circuits.

Current technical limits generally restrict the number of rows to around 128 or 160.

This is why most PMOLED screens on the market have pixel counts in ranges like 256 x 64 or 128 x 128 and cannot easily scale to high-definition resolutions like LCD or AMOLED.

Cathode Separator Pillars

Why Etching is Not Feasible

After the ITO anodes are fabricated, engineers need to deposit multiple organic layers (HIL, HTL, etc.).

The total thickness of these organic films is usually only 100 to 150 nanometers, and they are extremely sensitive to moisture, oxygen, and various chemical solvents.

In conventional semiconductor processes, forming metal lines involves covering the whole layer with metal, applying photoresist, and then "washing away" (etching) the unwanted metal with strong acids or plasma.

In PMOLED, however, if acid etching is used after the aluminum cathode layer is deposited, the acid would instantly penetrate and dissolve the delicate organic layers below, ruining the panel.

Therefore, PMOLED cathode strips cannot be processed via "subtraction" after deposition; they must be formed into disconnected patterns automatically during the deposition process.

Inverted Trapezoidal Geometry

This is a micro-wall structure pre-fabricated on the substrate before evaporating the organic and metal layers.

The cross-section of this wall is not a rectangle or a regular trapezoid, but an inverted trapezoid (Undercut).

Top Wide, Bottom Narrow: The top width of the separator pillar must be greater than its bottom width. For example, if the bottom is 10 microns, the top might be 12 or 15 microns.
Overhang Structure: This size difference creates an inward-recessing "eave" on the sides. This overhang is the absolute physical prerequisite for disconnecting the current.
Height Requirement: The height of the separator pillar is usually controlled between 1 to 3 micrometers.

Shadow Effect Blocking Metal

When the substrate enters the vacuum evaporation chamber for cathode metal deposition, aluminum or magnesium-silver alloy is heated into gaseous atoms, which fly towards the substrate like rain from below.

Direct Injection Zone: Metal atoms fly in a straight line and land on the ITO pixel area, forming the normal cathode conductive layer.
Top Accumulation: Metal atoms also land on the top surface of the separator pillars, forming a useless metal "cap."
Shadow Zone: Only at the base of the separator pillar (the inward-recessing area of the inverted trapezoid) are the metal atoms blocked by the "eave" above.

Relying on this physical shadow, the metal film that would otherwise be continuous is forced to break.

Each metal strip on a row of pixels is physically isolated from adjacent rows without any chemical etching steps.

Deposition Location	Metal State	Electrical Function
Pixel Surface	Continuous film	Working Cathode
Separator Top	Isolated metal block	Floating (No electrical connection)
Separator Sidewall	No metal / Discontinuous	Open circuit (Insulated)

Pixel Gaps and Aperture Ratio

The existence of this mechanical structure irreversibly occupies the effective light-emitting area of the display.

To accommodate the inverted trapezoid separator, a sufficient safety distance must be kept between pixels.

Physical Footprint: A separator pillar with a width of 10 to 20 microns wastes at least the same amount of non-emitting space between every two rows of pixels.
Safety Margin: To prevent manufacturing errors from causing metal connections, a buffer zone of several microns is required on both sides of the separator.
Data Quantization: In a low-resolution screen with a pixel pitch of 200 microns, a 20-micron separator might only occupy 10% of the space. But in a high-resolution screen where the pitch shrinks to 50 microns, the same separator would take up 40% of the space, causing the aperture ratio to drop drastically.

Manufacturing Yield Risk Points

This is a purely physical structural gamble, where any micro-scale deviation leads to failure.

Failure to Disconnect (Short): If the photoresist development is insufficient, the inverted trapezoid angle isn't large enough, or the sidewalls aren't steep enough, metal atoms might "climb" the wall and deposit, leading to adjacent cathode rows being connected.
Over-disconnection (Dark Spots): If the overhang is too large or the pillar collapses, it might cause the edges of the pixel area to lack metal coverage, reducing the effective emitting area or causing poor contact.
Outgassing Issues: Separator pillars use photosensitive organic materials (usually polyimide or acrylic resin). In high-vacuum environments, if these materials aren't thoroughly baked and cured, they will slowly release internal gas or solvent molecules, leading to degradation.

Driving Method

If the vertical resolution of the screen is N rows, the actual lighting time for a single row is only 1/N of the total frame cycle (the duty cycle).

Taking a common 0.96-inch screen with 128-row resolution as an example: to maintain an average brightness of 100 nits visible to the human eye, the OLED material must withstand a peak brightness impact of 12,800 nits during the conduction instant.

This high-voltage (usually >15V) short-pulse working mode causes power consumption to increase exponentially as size increases, making it suitable only for display scenarios under 3 inches.

Pre-charge and Discharge

Lag Caused by Capacitance

An OLED pixel is stacked like a sandwich of an anode, organic layers, and a cathode.

Although the capacitance of a single pixel is only between 10 pF and 30 pF, a single data line (column) usually connects to 64 or 128 pixels.

Column Capacitance Accumulation: When the driver chip tries to light up a column, it faces a load that is the sum of all pixel capacitances in that column, which can total 2000 pF to 4000 pF.
RC Delay: When the driving current flows through ITO lines with a certain resistance (several kilo-ohms), the massive capacitive load produces an RC time constant delay.
Phenomenon: If a constant current is supplied directly, the voltage rises slowly. The pixel will not emit light until the voltage reaches the OLED turn-on threshold (usually 3V to 5V).

Forceful Current Injection

To counter the delay caused by capacitor charging, the driver chip performs a "Pre-charge" operation before outputting actual image data current.

The power management module inside the driver IC temporarily bypasses the constant current source and pulls the driving voltage up close to the power rail (e.g., 15V or higher) or outputs a current pulse several times the normal display current.

Specific parameter settings for this process:

Phase Duration: Usually lasts only 2 to 10 microseconds (us).
Goal: Use a large current (I) to fill the capacitor (C) in a very short time (dt), so that the voltage (V) across the pixel jumps rapidly. The logic is: the rate of voltage change depends on the ratio of current to capacitance.
Result: Pixel voltage instantly reaches the operating voltage (e.g., 10V) at the start of the scanning cycle.

Removing Residual Charge

If the charge is not bled off, the voltage will stay above the threshold, causing the pixel to continue emitting weak light during the next row's scanning time.

This residual charge causes two problems:

Ghosting: A blurry tail following moving images.
Impure Black Levels: Areas that should be completely black show a grayish background, destroying the infinite contrast characteristic of OLED.

The "Discharge" phase usually occurs at the end of a row scanning cycle. The driver chip connects all column data lines to ground (GND) via a low-impedance path or applies a reverse bias voltage.

Grounding: Rapidly pulls the anode voltage to 0V, forcing charges in the capacitor to dissipate through the ground line.
Reverse Bias: A more aggressive approach is to apply a negative voltage (e.g., -2V) to the pixel. This not only clears the charge but also accelerates the reset of carriers within the organic material, helping to extend the OLED material's lifespan.

Scanning Timing Breakdown

Within the microsecond-level row scanning cycle (Line Time), the driver chip is not outputting image data for the entire duration.

The actual current output is divided into three strict time slots.

Assuming a 64-row screen driven at 100Hz, the total time for a single row is about 156 microseconds:

Phase	Typical Duration	Description	Electrical State
1: Reset & Pre-charge	2 - 5 us	Preparation	Voltage surges, current peaks, pixel voltage instantly crosses threshold.
2: Data Drive	140 - 150 us	Display	Constant current source active, current stable (e.g., 200uA), pixel emits stable light.
3: Discharge & Dead Time	2 - 5 us	Cleanup	Voltage reversed or grounded, charge bleeds off, pixel turns off completely.

If pre-charge and discharge times are set too long, they squeeze the "Data Drive" time used for display, reducing overall screen brightness.

If set too short, it leads to insufficient response or ghosting. Engineers need to fine-tune these parameters in the driver IC registers based on screen size and panel capacitance.

Constant Current Control

Why Abandon Voltage Driving?

Once the turn-on voltage exceeds the threshold (usually about 3V), every 0.1V increase in voltage can cause the current to double.

If a constant voltage source were used, two unsolvable physical obstacles would arise:

Thermal Drift: OLED organic materials are very temperature-sensitive. As the panel temperature rises during operation, the internal resistance of the material drops. If voltage is kept constant, the drop in resistance causes the current to skyrocket.
Manufacturing Tolerances: Even within the same screen, pixels at different locations have slight thickness variations due to the deposition process. This means each pixel's turn-on threshold is not identical. Applying a uniform 5V to all pixels would result in some having 100uA and others 150uA, causing "Mura" (brightness spots).

External Resistor for Reference

The driver chip has hundreds of output channels (corresponding to the number of columns, e.g., 128).

It must ensure the output current of all 128 channels is perfectly consistent.

The chip usually relies on a single external high-precision resistor to set the global reference current. This pin is typically labeled IREF.

Reference Current Generation: The internal circuit applies a fixed bandgap voltage (usually 1.2V or 2V) across this resistor, creating a tiny reference current.
Current Mirror Amplification: A current mirror structure inside the chip "copies" and amplifies this tiny reference current by a fixed multiplier.
Output Distribution: The amplified current (e.g., 2mA) is then distributed to each column driver module.

Pulse Width Modulation (PWM) for Grayscale

In constant current mode, once a pixel is lit, its current amplitude is typically fixed (e.g., at 200uA).

How then are different grayscale levels like dark gray, light gray, and white displayed?

The answer is controlling the duration of the light emission, not the current magnitude.

Assuming the time to scan one row is 100us and the system supports 256 grayscale levels (8-bit):

Full Black (Gray 0): Current output time is 0 us.
Full Bright (Gray 255): Current output time is 100 us.
Medium Gray (Gray 128): Current output time is 50 us.

The driver chip contains a high-frequency counter and a digital comparator for each column.

When the counter value is less than the pixel's grayscale data, the current switch is ON; once it exceeds the value, it switches OFF.

Although the pixel turns off after 50us, the human eye integrates the light energy over time and perceives it as 50% brightness.

Amplitude Modulation as Auxiliary

Besides PWM, some high-end driver ICs support Amplitude Modulation as an auxiliary.

When screen brightness is extremely low, the PWM pulse width becomes very narrow (nanoseconds).

Due to capacitance effects, a pulse that is too narrow might result in the pixel not even turning on before the switch closes.

In such cases, the chip reduces the current amplitude of the constant current source.

Mode	Control Variable	Scenario	Pros	Cons
PWM Mode	Time	Normal display	Good linearity, accurate color	Detail loss at low brightness
Analog Dimming	Amplitude (Gain)	Global brightness adjustment	Reduces power consumption	Susceptible to interference, non-uniform at low current

Overcoming Line Voltage Drop

In a passive matrix, current must flow through long ITO transparent electrodes. ITO is not a perfect conductor, with a sheet resistance of 10 to 30 ohms/square.

Remote Attenuation: Pixels farther from the driver interface have longer lines and higher resistance.
Constant Current Advantage: With voltage driving, remote pixels would get less voltage due to line division, making the far side of the screen dim. However, with constant current driving, the source automatically increases its output voltage (Compliance Voltage) to overcome the drop (IR drop) caused by line resistance.
Voltage Margin: As long as the required driving voltage does not exceed the chip's power rail limit (VCC, usually 12V-18V), the constant current source ensures the current flowing through near-end and far-end pixels is identical, completely eliminating brightness gradients caused by wiring length.

Pixel Control

The driver IC controls pixels by scanning the orthogonal anode and cathode strips row by row.

Due to the lack of Thin Film Transistors (TFT) to lock the charge, pixels are only conductive and emitting light at the instant the scanning line is selected

To maintain a human-perceivable average brightness of 100 to 200 nits, the diodes must operate at a peak current dozens of times higher than the average.

This high instantaneous power requirement physically limits the practical resolution of PMOLED to approximately 128 rows.

Cross-Grid Addressing

Electrode Physical Layer Stacking

From a microscopic perspective, the PMOLED display area is a grid "woven" from two layers of conductive materials.

Bottom Anode Layer: Usually fabricated on a glass substrate, typically using Indium Tin Oxide (ITO). These lines are etched into horizontal strips, usually defined as "Rows."
Organic Material Interlayer: On top of the anode, multiple layers of organic molecular films (HIL, EML, ETL) are deposited via vacuum evaporation. This layer is extremely thin, usually 100 to 200 nanometers.
Top Cathode Layer: Located at the very top, usually made of Aluminum or alloys. These metal strips are arranged vertically to the anodes, defined as "Columns."

Diode Rectification Characteristics

Every intersection point is electrically equivalent to a Light Emitting Diode.

The control logic relies entirely on the unidirectional conductivity (rectification) of the diode. To light up a pixel at (Row A, Col B), specific conditions must be met:

Forward Bias: Row A is connected to a high potential (e.g., 15V), and Col B to a low potential (e.g., 0V).
Threshold Breach: The potential difference between the anode and cathode must exceed the turn-on voltage (Vth, ~3V to 5V) of the OLED material.
Current Injection: Once the voltage difference is met, holes and electrons are injected from the anode and cathode respectively, recombining in the organic layer to emit light.

Losses from Line Resistance

Compared to aluminum, ITO's sheet resistance is much higher (10-30 ohms/sq).

In a long PMOLED screen, current travels from the driver chip along thin ITO strips to remote pixels, causing a significant voltage drop (IR Drop).

Voltage Loss: If an entire row of pixels is lit, the total current can reach dozens of milliamps. According to Ohm's Law, the ITO line resistance consumes part of the voltage.
Non-uniform Brightness: Since OLED brightness is related to current, small voltage differences cause noticeable brightness decay. One side of the screen may look dimmer than the other.
Compensation: Engineers widen electrode lines or use pre-emphasis techniques in the driver algorithm to provide higher initial voltage to far-end pixels.

Capacitance Effect at Intersections

The cross-grid is also a massive capacitor array. Each pixel fits the definition of a parallel plate capacitor (two conductors sandwiching a semiconductor).

Parasitic Capacitance: While a single pixel's capacitance is small (pF), a whole row of 128 or 256 pixels in parallel accumulates to nanofarad (nF) levels.
RC Delay: Resistance (R) and capacitance (C) form a low-pass filter. Square wave signals for lighting pixels don't rise vertically but climb slowly like a shark fin.
Refresh Rate Limit: If scanning is too fast, the cycle ends before the capacitor is fully charged, and the pixel fails to reach target brightness.

Reverse Leakage and Crosstalk

If (Row 1, Col 1) and (Row 2, Col 2) are lit, current might leak through surrounding pixels like (Row 1, Col 2) if potentials aren't managed, causing unintended glowing.

To block this, "Reverse Bias" is used: non-selected rows are forced to a reverse voltage or grounded, ensuring non-selected diodes remain in a deep cutoff state.

Progressive Scanning Mechanism

Frame Rate and Row Cycle Calculation

Standard displays run at 60Hz to 100Hz. At 60Hz, a full frame takes 16.6ms. For a 64-row PMOLED:

Row Cycle: 16.6ms / 64 ≈ 260 microseconds per row.
Duty Cycle Limit: At 128 rows, the cycle shrinks to 130us.
Effective Time: Actual light-emitting time is even shorter after subtracting signal switching and pre-charge/discharge "dead zones."

Three Phases of a Scanning Cycle

Pre-charge Phase: To counter physical delay, the driver applies a high-voltage pulse in the first 5-10% of the row cycle to fill capacitors quickly.
Driving Phase: The actual emission phase (85% of the cycle). Row drivers pull the line to potential while column drivers output constant current.
Discharge Phase: In the last 5% of the cycle, electrodes are shorted to ground to clear residual charge, ensuring pure blacks and preventing ghosting.

Shift Register Logic

Scanning is controlled by a chain of flip-flops. A "Start Pulse" acts as a token, moving from Row 1 to Row 2 with each clock signal.

When the N-th register holds the token, its power stage activates the physical circuit for that row.

Column data for that row must be pre-loaded in a "Line Buffer" to stay synchronized.

Flicker and Refresh Rate Trade-off

Below 50Hz, the eye perceives flicker. While increasing to 100Hz+ eliminates this, it shortens the row cycle, making RC constants more problematic and requiring even higher instantaneous current, which accelerates thermal degradation of the OLED material.

Duty Cycle and Brightness

Calculation of Duty Cycle

Inverse Resolution Law: For N rows, the theoretical max duty cycle is 1/N.
Dead Zone Loss: Engineering realities usually limit it to 1/(N+2) or 1/(N+8). For 128 rows, the pixel is off for over 99.2% of the time.

Peak vs. Average Brightness Conversion

Because the eye integrates light over time, the peak brightness must be huge: Peak Brightness = Average Brightness / Duty Cycle.

For 150 nits average on a 128-row screen, the peak must be 19,200 nits. This is 20 times higher than typical mobile AMOLED peak brightness.

Non-linear IV/LI Relationship

Current Density: To get 20,000 nits, current density might exceed 200 mA/cm², compared to 10 mA/cm² for AMOLED.
Voltage Penalty: To drive such current, voltage must rise to 15V-20V. Since Power = VI, a 10x increase in current and 2x increase in voltage results in 20x the power consumption.

Accelerated Aging

Joule Heating: Massive current creates heat that cannot dissipate fast enough, breaking organic molecular bonds.
Coulombic Aging: Aging is non-linear; driving at 10x current for 1/10th of the time is much more damaging than 1x current for 100% of the time.
Burn-in: Static icons subject pixels to constant high-pressure pulses, causing them to dim faster and leave permanent "ghost images."